Background of Related Art
Semiconductor devices that have integrated circuits are produced by fabricating a large plurality of identical circuit patterns on a semiconductor wafer or other bulk substrates of semiconductor material, wherein each circuit pattern defines a die. A plethora of conventional processes is typically used, including for example, doping, photolithography, layering, etching, laser ablation, metallization, oxidation, layer removal, wafer thinning/planarization, die separation and packaging. Inasmuch as the major goals of semiconductor manufacturers generally typify increased performance and lower cost, considerations such as device density (with concomitant increased circuit speed and reduced power requirements) and enhanced reliability have taken a high priority. In addition, it may be increasingly important that repetitive operations be performed on an entire wafer prior to die separation (singulation), to speed production, reduce production costs, and increase semiconductor device uniformity and reliability and, ultimately, yield.
One way to increase the density of semiconductor devices in a semiconductor assembly is to stack semiconductor dice one upon another. The stacked semiconductor dice may be interconnected by forming conductive vias in through holes in one or more of the semiconductor dice. An interior of each of the vias may be coated with an electrical isolation material followed by an electrically conductive material to electrically connect the vias to integrated circuitry fabricated on an active surface of the semiconductor die and to form a plurality of hollow through-hole vias. Thus, the vias may provide a conductive pathway from the active surface of a semiconductor die to its back surface, enabling interconnection of vias on the back surface, the active surface, or both surfaces of the semiconductor die to external electrical contacts of another semiconductor die or to a carrier substrate. Through holes are typically formed by etching, laser ablation, or a combination thereof. In an etching method, photolithographic patterning of a photoresist is used to define the via locations, followed by wet (chemical) or dry (reactive ion) etching. Laser drilling has been used to form vias by ablating semiconductor material to form through holes extending through the entire thickness of a semiconductor die. The laser-drilled via may then be etched to clean slag from the via and smooth its walls.
Various conductive structures on a die or wafer may be interconnected by a conductive via and further through at least one of bond pads, component leads, metal wires, metal layers, and annular rings. Bond pads on semiconductor dice are typically formed from tungsten, aluminum, copper, or aluminum-copper alloys ranging from 1.5 to 1.0% or less copper. When formed of aluminum, the bond pads may be plated with nickel to deter oxidation and provide a solder-wettable surface. However, a layer of oxide may also form upon nickel, though not as rapidly as aluminum. Such a layer of nickel oxide may present a problem with adhesion or wetting of a molten metal (e.g., solder) thereto.
One of the problems encountered in the use of high density ball grid arrays (BGA), column grid arrays (CGA), or chip scale packaging (CSP) may occur when a through-wafer interconnect (TWI) of a substrate is connected to another substrate such as an electronic module or circuit board. Particularly, when the solder deposited on a bond pad is associated with a hollow conductive via and is heated to a reflow temperature, molten solder may be wicked into the hollow through hole, depleting the ball of sufficient solder to complete the conductive connection.
U.S. Pat. No. 5,275,330 to Isaacs et al. describes a method for improving the connection of hollow through-hole vias in a printed circuit board (PCB) to an electronic module. As shown in this reference, each via is filled step-wise until completely filled with solder, prior to placement and attachment of solder balls of a module. However, multiple pass solder-plugging steps are required and assembly yield may be lower than desired. This method may sometimes result in other problems, including molten/softened solder drainage from the via by gravity or other influences and replacement by solder drawn from the solder ball attachment, compromising the solder ball electrical connection.
As shown in U.S. Pat. No. 6,076,726 to Hoffmeyer et al., it is proposed to plate the cylindrical via with a metal, such as nickel, which may not be wetted effectively by the reflowing of a lead-tin eutectic solder while using fluxes that allow effective wetting to copper. The bond pad of the via is copper plated to effect good wetting to a solder ball. The goal of the reference is to form a hollow (cylindrical) via which is not wettable for solder adhesion, while allowing the bond pad to be wetted by solder.
As described in U.S. Pat. No. 5,734,560 to Kamperman et al., hollow plated through holes in a multi-layer circuit board are capped with a multi-layer cap to prevent the flow of solder into the through holes. The caps comprise a conductive layer attached to one or more insulating layers. The caps are configured in a sheet which may be attached over the field of through holes. However, as an impediment to implementation of such a configuration, cap locations on the sheet must be precisely positioned so as to be aligned with respective through holes.
In U.S. Pat. No. 4,383,363 to Hayakawa et al., a solder paste is used to interconnect the conductive planes on either of a printed circuit board through a via hole. The via hole is not plated and the solder paste is not reflowed. Conductive layers deposited on the substrate and over the via entrap the solder paste within the via hole. Because the solder paste is not reflowed, electrical continuity is established through particle-to-particle contact, which is not always reliable.
There are fundamental differences in forming vias in a circuit board and forming vias in a semiconductor wafer which contains many discrete microchip circuits. While a circuit board is typically manufactured at a desired final thickness, semiconductive materials such as silicon and the like are fragile materials subject to easy fracture. Thus, in contrast to circuit board fabrication, fabrication of electronic devices on an entire semiconductor wafer is typically conducted before the wafer is thinned by a chemical mechanical process (CMP) or back grinding to a desired final thickness. None of the above referenced patents refer to the formation of a conductive via or TWI in a semiconductor wafer such as comprising a plurality of integrated circuits or the like.
In light of efforts to overcome the disadvantages of the prior art, it may be appreciated that it would be advantageous to develop improved methods for forming TWIs through a semiconductor wafer.